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| Ordering number : EN *5194D CMOS LSI (P-sub) LC4104C LCD Dot Matrix Segment Driver for STN Displays Preliminary Overview The LC4104 is a segment driver LSI for large-scale dot matrix LCD displays. The LC4104 latches 160-bits of display data transferred from the controller over a 4- or 8bit parallel interface and generates the LCD drive signals. In conjunction with the LC4102 common driver, the LC4104 forms a chip set that can drive large-screen LCD panels. Features * * * * * * * * * * * High-voltage CMOS (P-sub) process LCD drive voltage: 36 V Logic system power-supply voltage: 2.7 to 5.5 V Maximum fcp: 12 MHz (VDD = 5 V 10%), 10 MHz (VDD = 2.7 to 4.5 V) Slim chip (The output pads are located along one of the long sides.) Parallel input circuit can be switched between 4 and 8 bits. Output directionality switching DISPOFF function (Holds the LCD drive voltage at a fixed level.) Display duty ratios: 1/160 to 1/480 Appropriate for COG (chip on glass) mounting. (A gold bump structure is adopted in the pad areas.) LC4104C: Chip product SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 43098HA (OT)/73097HA (OT)/D3095HA (OT) No. 5194-1/9 LC4104C Block Diagram Specifications The following electrical characteristics apply when sealed in a Sanyo standard PGA-208 package. Absolute Maximum Ratings at VSS = 0 V Parameter Maximum supply voltage Maximum supply voltage Maximum supply voltage Input voltage Input voltage Input voltage Input voltage Operating temperature Storage temperature Symbol VDD max VDDH max VSS max VIN V0, V2 V3 V5 Topr Tstg D0 to D7, LOAD, CP, R/L, TEST, DISP, M, EIO1, EIO2, BS V0, V2 V3 V5 Conditions min -0.3 -0.3 -0.3 -0.3 VDDH - 7 -0.3 -0.3 -20 -55 typ max 7 40 +0.3 VDD + 0.3 VDDH + 0.3 VSS + 7 +0.3 +75 +125 Unit V V V V V V V C C Note: V0, V2, V3, and V5 must obey the following inequalities: VDDH V0 V2 VDDH - 7 V, and 7 V V3 V5 VSS. No. 5194-2/9 LC4104C Allowable Operating Ranges at Ta = -20 to +75C, VSS = 0 V Parameter Supply voltage Supply voltage Supply voltage Input high-level voltage Input low-level voltage Input voltage Input voltage Input voltage Symbol VDD VDDH VSS VIH VIL V0, V2 V3 V5 D0 to D7, LOAD, CP, R/L, M, TEST, DISP, BS, EIO1, EIO2 D0 to D7, LOAD, CP, R/L, M, TEST, DISP, BS, EIO1, EIO2 V0, V2 V3 V5 0.8 VDD 0 VDDH - 7 0 0 Conditions min 2.7 20 0 VDD 0.2 VDD VDDH VSSH + 7 typ max 5.5 36 Unit V V V V V V V V Note: V0, V2, V3, and V5 must obey the following inequalities: VDDH V0 V2 VDDH - 7 V, and 7 V V3 V5 VSS. At power on: First turn on the logic system power supply and then turn on the high-voltage system power supply. At power off: First turn off the high-voltage system power supply and then turn off the logic system power supply. Allowable Operating Ranges at Ta = -20 to +75C, VSS = 0 V, VDD = 5 V 10% Parameter CP clock frequency High-level load pulse width High-level clock pulse width Low-level clock pulse width LOAD/CP setup time LOAD/CP hold time DATA/CP setup time DATA/CP hold time EIO input setup time Clock rise time Clock fall time Symbol fcp tw (ldH) tw (cpH) tw (cpL) tsu (ld) tho (ld) tsu (cp) tho (cp) tsu (ei) tr tf CP LOAD CP CP LOAD, CP LOAD, CP CP, D0 to D7 CP, D0 to D7 CP, EIO1, EIO2 LOAD, CP* LOAD, CP* 50 20 20 100 200 10 10 24 50 50 Conditions min typ max 12 Unit MHz ns ns ns ns ns ns ns ns ns ns Note: * The clock rise time (tr) and fall time (tf) must obey inequalities and y below. 1 - tw (cph) - tw (cpl) fcp : tr, tf < 2 y: tr, tf 50 ns Allowable Operating Ranges at Ta = -20 to +75C, VSS = 0 V, VDD = 2.7 to 4.5 V Parameter CP clock frequency High-level load pulse width High-level clock pulse width Low-level clock pulse width LOAD/CP setup time LOAD/CP hold time DATA/CP setup time DATA/CP hold time EIO input setup time Clock rise time Clock fall time Symbol fcp tw (ldH) tw (cpH) tw (cpL) tsu (ld) tho (ld) tsu (cp) tho (cp) tsu (ei) tr tf CP LOAD CP CP LOAD, CP LOAD, CP CP, D0 to D7 CP, D0 to D7 CP, EIO1, EIO2 LOAD, CP* LOAD, CP* 50 37 37 100 200 35 35 30 50 50 Conditions min typ max 10 Unit MHz ns ns ns ns ns ns ns ns ns ns Note: * The clock rise time (tr) and fall time (tf) must obey inequalities and y below. 1 - tw (cph) - tw (cpl) fcp : tr, tf < 2 y: tr, tf 50 ns No. 5194-3/9 LC4104C Electrical Characteristics at Ta = -20 to +75C, VDD = 2.7 to 5.5 V, VSS = 0 V Parameter Input high-level current Symbol IIH IIL1 Input low-level current IIL2 Output high-level voltage Output low-level voltage Output on resistance VOH VOL ROUT IDD Current drain IDDH IST Conditions VIN = VDD: D0 to D7, LOAD, CP, R/L, M, DISP, EIO1, EIO2, BS, TEST VIN = VSS: D0 to D7, LOAD, CP, R/L, M, TEST, DISP, EIO1, EIO2, BS VIN = VSS: TEST IO = -0.4 mA: EIO1, EIO2 IO = 0.4 mA: EIO1, EIO2 VDDH = 36 V*1, V0 - VO = 0.5 V, V2 - VO = 0.5 V, VO - V3 = 0.5 V, VO - V5 = 0.5 V: O1 to O160 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V, VDDH = 32 V*2, VDD = 5 V 10%, VDDH = 36 V *3 -5 A -500 VDD - 0.4 VSS 1 VDD 0.4 3 5.0 2.0 2.0 500 V V k mA mA mA A min typ max 5 Unit A Note: 1. VO is the voltage applied for an on output, V0 = VDDH, V2 = 18/20 (VDDH - VSS), V3 = 2/20 (VDDH - VSS), V5 = VSS 2. LOAD = 28 kHz, CP = 10 MHz, M = 75 Hz Alternatively: No output load and with the inputs VIH = VDD and VIL = VSS. 3. The current drain in standby mode. Note that the EIOn pins must be held at VDD. Switching Characteristics at Ta = -20 to +75C, VSS = 0 V, VDD = 5 V 10% Parameter EIO output delay time LD/EIO output delay time LOAD/on delay time M/on delay time Symbol td (eo) td (leo) td (ldo) td (mo) Conditions 30 pF capacitive load: CP, EIO1, EIO2 30 pF capacitive load: LOAD, EIO1, EIO2 100 pF capacitive load: LOAD, O1 to O160 100 pF capacitive load: M, O1 to O160 min typ max 40 70 700 700 Unit ns ns ns ns Switching Characteristics at Ta = -20 to +75C, VSS = 0 V, VDD = 2.7 to 4.5 V Parameter EIO output delay time LD/EIO output delay time LOAD/on delay time M/on delay time Symbol td (eo) td (leo) td (ldo) td (mo) Conditions 30 pF capacitive load: CP, EIO1, EIO2 30 pF capacitive load: LOAD, EIO1, EIO2 100 pF capacitive load: LOAD, O1 to O160 100 pF capacitive load: M, O1 to O160 min typ max 80 130 3 3 Unit ns ns s s Timing Chart No. 5194-4/9 LC4104C Pin Functions Symbol I/O LCD drive outputs M H O1 to O160 O H L L * Data H L L H * DISP H H H H L On V0 V2 V3 V5 V5 Function *: Don't care. (Must be held either high or low.) V0 V2 V3 V5 VDDH VDD VSS DISP M I I I I V0 level drive voltage supply (selected level) V2 level drive voltage supply (unselected level) V3 level drive voltage supply (unselected level) V5 level drive voltage supply (selected level) Pins with the same name must be set to the same potential. -- -- -- I I High-voltage system power supply. Pins with the same name must be set to the same potential. Logic system power supply. GND LCD off function. All outputs go to the V5 level when this pin is low. Alternation signal input Enable I/O R/L EIO1 In Out EIO2 Out In EIO1 EIO2 I/O I/O L H Enable input: The enable input at the first stage is fixed at VSS. For succeeding stages, the enable input is connected to the enable output from the preceding stage. Enable output: Connected to the enable input of the next stage when cascode connection is used. CP LOAD TEST I I I Data acquisition clock (falling edge) Data load clock (falling edge) Test input. Must be tied high in normal use.* Data shift direction setting R/L L H R/L I H BS O1 D7 O1 D0 O1 D3 O1 D0 O2 D6 O2 D1 O2 D2 O2 D1 O3 D5 O3 D2 O3 D1 O3 D2 O1 to O160 outputs O4 D4 O4 D3 O4 D0 O4 D3 ... O157 D3 O157 D4 O157 D3 O157 D0 O158 D2 O158 D5 O158 D2 O158 D1 O159 D1 O159 D6 O159 D1 O159 D2 O160 D0 O160 D7 O160 D0 O160 D3 . . . ... L L H . . . D0 to D7 BS I I Parallel data inputs Input bus setting. Set high for 8-bit input, low for 4-bit input. For 4-bit input, D0 to D3 are used for data input and D4 to D7 must be tied to ground. Note: * This IC is sensitive to ESD care must be used when handling this device. No. 5194-5/9 LC4104C Pin Assignment No. 5194-6/9 LC4104C Pad Coordinates PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 O24 O25 O26 O27 O28 O29 O30 O31 O32 O33 O34 O35 O36 O37 O38 O39 O40 X coordinate -6360.0 -6280.0 -6200.0 -6120.0 -6040.0 -5960.0 -5880.0 -5800.0 -5720.0 -5640.0 -5560.0 -5480.0 -5400.0 -5320.0 -5240.0 -5160.0 -5080.0 -5000.0 -4920.0 -4840.0 -4760.0 -4680.0 -4600.0 -4520.0 -4440.0 -4360.0 -4280.0 -4200.0 -4120.0 -4040.0 -3960.0 -3880.0 -3800.0 -3720.0 -3640.0 -3560.0 -3480.0 -3400.0 -3320.0 -3240.0 Y coordinate 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 PAD No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Signal O41 O42 O43 O44 O45 O46 O47 O48 O49 O50 O51 O52 O53 O54 O55 O56 O57 O58 O59 O60 O61 O62 O63 O64 O65 O66 O67 O68 O69 O70 O71 O72 O73 O74 O75 O76 O77 O78 O79 O80 X coordinate -3160.0 -3080.0 -3000.0 -2920.0 -2840.0 -2760.0 -2680.0 -2600.0 -2520.0 -2440.0 -2360.0 -2280.0 -2200.0 -2120.0 -2040.0 -1960.0 -1880.0 -1800.0 -1720.0 -1640.0 -1560.0 -1480.0 -1400.0 -1320.0 -1240.0 -1160.0 -1080.0 -1000.0 -920.0 -840.0 -760.0 -680.0 -600.0 -520.0 -440.0 -360.0 -280.0 -200.0 -120.0 -40.0 Y coordinate 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 Continued on next page. No. 5194-7/9 LC4104C Continued from preceding page. PAD No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Signal O81 O82 O83 O84 O85 O86 O87 O88 O89 O90 O91 O92 O93 O94 O95 O96 O97 O98 O99 O100 O101 O102 O103 O104 O105 O106 O107 O108 O109 O110 O111 O112 O113 O114 O115 O116 O117 O118 O119 O120 X coordinate 40.0 120.0 200.0 280.0 360.0 440.0 520.0 600.0 680.0 760.0 840.0 920.0 1000.0 1080.0 1160.0 1240.0 1320.0 1400.0 1480.0 1560.0 1640.0 1720.0 1800.0 1880.0 1960.0 2040.0 2120.0 2200.0 2280.0 2360.0 2440.0 2520.0 2600.0 2680.0 2760.0 2840.0 2920.0 3000.0 3080.0 3160.0 Y coordinate 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 PAD No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Signal O121 O122 O123 O124 O125 O126 O127 O128 O129 O130 O131 O132 O133 O134 O135 O136 O137 O138 O139 O140 O141 O142 O143 O144 O145 O146 O147 O148 O149 O150 O151 O152 O153 O154 O155 O156 O157 O158 O159 O160 X coordinate 3240.0 3320.0 3400.0 3480.0 3560.0 3640.0 3720.0 3800.0 3880.0 3960.0 4040.0 4120.0 4200.0 4280.0 4360.0 4440.0 4520.0 4600.0 4680.0 4760.0 4840.0 4920.0 5000.0 5080.0 5160.0 5240.0 5320.0 5400.0 5480.0 5560.0 5640.0 5720.0 5800.0 5880.0 5960.0 6040.0 6120.0 6200.0 6280.0 6360.0 Y coordinate 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 825.0 Continued on next page. No. 5194-8/9 LC4104C Continued from preceding page. PAD No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 Signal V5 NC V3 NC VDDH NC V2 NC V0 NC D0 NC D1 NC D2 NC D3 NC D4 NC D5 NC D6 NC D7 NC VDD NC EIO2 NC X coordinate 6300.0 6075.0 5850.0 5625.0 5400.0 5175.0 4950.0 4725.0 4500.0 4275.0 4050.0 3825.0 3600.0 3375.0 3150.0 2925.0 2700.0 2475.0 2250.0 2025.0 1800.0 1575.0 1350.0 1125.0 900.0 675.0 450.0 225.0 0.0 -225.0 Y coordinate -825.0 -825.0 -825.0 -825.0 -825.0 -800.0 -800.0 -800.0 -800.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 PAD No. 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 Signal EIO1 NC CP NC LOAD NC M NC DISP NC TEST NC R/L NC BS NC VSS NC VDDH NC V0 NC V2 NC V3 NC V5 X coordinate -450.0 -675.0 -900.0 -1125.0 -1350.0 -1575.0 -1800.0 -2025.0 -2250.0 -2475.0 -2700.0 -2925.0 -3150.0 -3375.0 -3600.0 -3825.0 -4050.0 -4275.0 -4500.0 -4725.0 -4950.0 -5175.0 -5400.0 -5625.0 -5850.0 -6075.0 -6300.0 Y coordinate -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -800.0 -800.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 -825.0 s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: y Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of April, 1998. Specifications and information herein are subject to change without notice. PS No. 5194-9/9 |
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